1. Field of the Invention
The present invention relates to a data transfer control device for controlling data transfer operations performed between memories, a semiconductor memory device including the same data transfer control device, and an electronic information apparatus including the semiconductor memory device.
2. Description of the Related Art
Conventionally, unlike a memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) which loses data stored therein when turned off, a nonvolatile semiconductor memory device (a nonvolatile memory) is characterized in that data stored in memory cells of the nonvolatile memory is not lost even when turned off. In addition to a flash memory which is now in wide use in mobile phones or the like, examples of the nonvolatile memory include FRAM (Ferro-Electric Random Access Memory) which is recently coming into use in IC cards or the like, MRAM (Magnetic Random Access Memory) which is being intensively developed, etc.
Nonvolatile memory and in particular flash memory are described herein.
Generally, in a flash memory, operation speed of a read operation, a write operation including a verify operation and an erase operation including a verify operation becomes slower for this order of operations. The read operation requires about 100 nanoseconds (nsec), the write operation including a verify operation requires about 30 microseconds (is), and the erase operation including a verify operation requires about 500 milliseconds (msec). That is, in the flash memory, the write and erase operations require extraordinary time as compared to the read operation.
On the other hand, a volatile semiconductor memory device representative of a DRAM and an SRAM is disadvantageous in that stored information is lost when turned off. However, the nonvolatile semiconductor memory device has a feature that a period of time required for the write operation is substantially equivalent to a period of time required for the read operation. For example, an SRAM completes each of the read and write operations in about 100 ns. That is, the SRAM can rewrite data in a period of time which is considerably short as compared to a period of time required for the write or erase operations of the flash memory.
Conventionally, a page buffer technique has been used for compensating for the disadvantage of the flash memory of the long time period required for the write operation. In the case where a central processing unit (CPU) processes data, since the write operation of the flash memory requires a long period of time, a latent period of a CPU is inevitably lengthened. When a large quantity of data is being written in the flash memory, the CPU cannot perform another process during the write operation.
Accordingly, a method has been utilized for apparently shortening the period of time required for the write operation by realizing a semiconductor memory device having a function of initially writing data in a nonvolatile semiconductor memory device called a page buffer, such as an SRAM in which a period of time required for the write operation is short, and then transferring batches of data from the nonvolatile semiconductor memory device to the flash memory. This releases the CPU from the data write operation on the flash memory which requires a long period of time, and thus can perform another process.
In this page buffer technique, an address in the page buffer is mirrored at an arbitrary address in the flash memory. Therefore, in a command sequence at the time of writing the data in the page buffer, a CPU issues a page buffer write command in the first cycle, inputs the number of batches of transfer data (hereinafter, referred to as xe2x80x9ctransfer data numberxe2x80x9d) in the page buffer in the second cycle, and inputs as an operand of the command a set of an address in the flash memory and a batch of data to be written in the page buffer in the third cycle. This operation in the third cycle is repeatedly performed in the later cycles until sets of an address and a batch of transfer data are input such that the number of the sets corresponds to the transfer data number input in the second cycle. A CPU issues a confirmation command in the last cycle.
By extracting the transfer data number from this command sequence in the second cycle and by extracting a transfer start address from the command sequence and storing the extracted transfer start address in the page buffer in the third cycle, a write state machine (which is a circuit for controlling internal operations of the memory device and is also referred herein to as xe2x80x9cWSMxe2x80x9d) uses the data, i.e., command information on the transfer data number, the transfer start address, etc., so as to perform a data transfer operation from the page buffer to the flash memory.
FIG. 9 shows an example of a primary structure of an address control circuit for use with the page buffer technique. In FIG. 9, when a command to transfer data is externally input to the WSM, the WSM controls an address control circuit 105 so as to start data transfer from the page buffer to the flash memory. This data transfer operation is further described in detail below.
As shown in FIG. 9, before starting the data transfer operation, the WSM controls the address control circuit 105 so as to store in a memory address register 100 the data transfer start address in the input command information via an external address pad A and store the transfer data number via a data pad D in a transfer data number register 102.
Next, the WSM controls the memory address register 100 so as to transfer the stored data transfer start address of the flash memory to a memory address counter 101 via a transfer bus 120 connected between the memory address register 100 and the memory address counter 101. This allows a flash memory array decoder 121 to perform a decode operation such that an address in a flash memory array to which data is transferred is set so as to be a data transfer start address while allowing a page buffer decoder 122 to perform a decode operation such that an address in the page buffer from which the data is transferred is set so as to be a transfer start address, i.e., a first address at which data to be written in the flash memory array is stored.
Next, a data counter 103 is reset so as to have an initial value. Then, the WSM accesses a memory cell selected according to the decoded address so as to read data from the page buffer and write the data in a memory cell at a transferee address in the flash memory.
This operation realizes a data write operation from the page buffer to the flash memory. When the data write operation from the page buffer to the flash memory is completed with respect to the decoded address, the WSM increments the memory address counter 101 such that an address of each of the page buffer and the flash memory is updated so as to be the next address (an address obtained by adding one bit to the current address). Similarly, the data counter 103 is incremented.
As described above, the WSM reads data at the updated address of the page buffer and writes the data in a memory cell corresponding to the updated address of the flash memory.
This operation is repeatedly performed. A comparison circuit 111 compares a value stored in the data counter 103 with a value latched by the data counter 103 which is the transfer data number in put from the WSM. When the comparison results in a match, the WSM detects that a final address is obtained, thereby completing the data transfer from the page buffer to the flash memory.
As devices using the page buffer technique described above, a semiconductor memory device which can reduce a decrease in data transfer rate by reducing overhead during data transfer (Japanese Laid-Open Patent Publication No. 11-85609, xe2x80x9cSEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANAGING DATA STORED THEREINxe2x80x9d), and a memory device which can realize high-speed write access to data along with low power consumption (Japanese Laid-Open Patent Publication No. 10-283768, xe2x80x9cMEMORY DEVICE AND METHOD FOR CONTROLLING DATA RECEPTION WHEN CLOCK OSCILLATION IS CEASEDxe2x80x9d) have been suggested.
Further, there is a method of data transfer between two memories which is referred to as a direct memory access (DMA) method in which data is transferred from one memory to another. In the direct memory access method, a transfer start address is written in a memory address register via a direct memory access controller circuit and the number of words to be transferred is written in a word count register via a control circuit. After memory address data corresponding to the address of the memory address register is transferred to another memory, the memory address register is counted up so as to increase a value stored in the memory address register by xe2x80x9c1xe2x80x9d and the word count register is counted down so as to decrease a value stored in the word count register by xe2x80x9c1xe2x80x9d. This operation is repeatedly performed until a value stored in the word counter register becomes zero.
As the direct memory access method described above, a memory addressing method which can reduce the quantity of hardware and reduce the load on software (Japanese Laid-Open Patent Publication No. 58-166581) has been suggested.
In a data write operation using the conventional page buffer described above, data is temporally stored in the page buffer having a fast writing speed and batches of data are transferred together from the page buffer to the flash memory. This data transfer method is intended to shorten the period of time required for writing data in the flash memory.
However, in this page buffer technique, an address in the page buffer is mirrored at an arbitrary address in the flash memory, and therefore there is no specific address in the page buffer, so that mutual data transfer cannot be performed. Therefore, in the page buffer technique, it is also not possible to read specific data written in the page buffer.
On the other hand, in the direct memory access, method, an access controller performs data transfer between two memory arrays separately provided on different semiconductor chips, and therefore the number of semiconductor chips required for data transfer is increased, thereby increasing an area on which the semiconductor chips are mounted. Further, there is a problem that the duration of the data transfer is long since the data transfer is performed between different semiconductor chips.
In view of these problems, a semiconductor memory device in which a plurality of memory arrays are provided so as to be individually operable, and mutual data transfer between the memory arrays can be performed simultaneously as performing data read/write operations on respective memory arrays (Japanese Patent Application No. 2000-176182) has been suggested.
However, in such a semiconductor memory device, in order to perform data transfer, separate circuits are provided so as to perform data transfer from a first memory array to a second memory array or vice versa, and therefore it is not considered to commonly use data between circuits. Therefore, a layout area of a semiconductor chip is increased by, for example, providing plural sets of memory address registers exclusively used for each memory array according to an implementation method.
According to one aspect of the present invention, there is provided a data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command and data transfer start addresses and a data transfer completion address of the first and second memory arrays, the device includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section; and a first comparison target address switch section for performing a switching operation from a memory address targeted for comparison with the data transfer completion address to a memory address corresponding to either the first or second memory arrays so as to detect the completion of the data transfer based on the input control command, and the mutual transfer between the first and second memory arrays is performed based on sequentially-incremented address values of the first and second memory address storage sections.
According to another aspect of the present invention, there is provided a data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command and each of data transfer start addresses and data transfer completion addresses of the first and second memory arrays, and the device includes: a command recognition section for recognizing the input control command: a first address output section for outputting a data transfer start address of the first memory array, a data transfer completion address of the first memory array, and a data transfer start address of the second memory array based on the input control command in this storage order or outputting the data transfer start address of the second memory array, data transfer completion address of the second memory array and data transfer start address of the first memory array based on the input control command in this storage order; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a first memory address counter section for incrementing a memory address for each unit of data transfer; a first memory address transfer section for transferring the data transfer start address from the first memory address storage section to the first memory address counter section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a second memory address counter section for incrementing a memory address for each unit of data transfer; a second memory address transfer section for transferring the data transfer start address from the second memory address storage section to the second memory address counter section; a third memory address storage section for storing the data transfer completion address output from the first address output section; a first comparison section for comparing a value of the data transfer completion address and a value of the first or second memory address counter section; a first comparison target address switch section for controlling a switch between values of the first and second memory address counter sections targeted for comparison to the data transfer completion address based on the input control command so as to compare the value of the data transfer completion address to any one of the values of the first and second memory address counter sections; and a first data transfer control section for performing the mutual data transfer between the first and second memory arrays based on address values set in the first and second memory address counter sections and completing the mutual data transfer based on a comparison result obtained by the first comparison section.
According to still another aspect of the present invention, there is provided a data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command, data transfer start addresses and a data transfer completion address of the first and second memory arrays, and the number of batches of data to be transferred, and the device includes: a command recognition section for recognizing the input control command; a second address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command: a first memory address storage section for storing the data transfer start address of the first memory array output from the second address output section: a second memory address storage section for storing the data transfer start address of the second memory array output from the second address output section; a transfer data number storage section for storing the number of batches of data to be transferred output from the second address output section; a data counter section for incrementing the number of batches of data for each data transfer unit; a second comparison section for comparing the number of batches of data to a value of the data counter section; and a second data transfer control section performing the mutual data transfer between the first and second memory arrays based on values obtained by sequentially incrementing address values of the first and second memory address storage sections and completing the mutual data transfer based on a comparison result obtained by the second comparison section.
According to still another aspect of the present invention, there is provided a data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command, data transfer start addresses and a data transfer completion address of the first and second memory arrays, and the number of batches of data to be transferred, and the device includes: a command recognition section for recognizing the input control command; a second address output section for outputting a data transfer start address of the first memory array, the number of batches of data to be transferred, and a data transfer start address of the second memory array based on the input control command in this storage order or outputting the data transfer start address of the second memory array, the number of batches of data to be transferred, and a data transfer start address of the first memory array based on the input control command in this storage order: a first memory address storage section for storing the data transfer start address of the first memory array output from the second address output section: a first memory address counter section for incrementing a memory address for each unit of data transfer: a first memory address transfer section for transferring the data transfer start address from the first memory address storage section to the first memory address counter section; a second memory address storage section for storing the data transfer start address of the second memory array output from the second address section; a second memory address counter section for incrementing a memory address for each unit of data transfer; a second memory address transfer section for transferring the data transfer start address from the second memory address storage section to the second memory address counter section; a transfer data number storage section for storing the number of batches of data to be transferred output from the second address output section; a data counter section for incrementing the number of batches of data for each data transfer unit; a second comparison section for comparing the number of batches of data to a value of the data counter section; and a second data transfer control section performing the mutual data transfer between the first and second memory arrays based on address values set in the first and second memory address counter sections and completing the mutual data transfer based on a comparison result obtained by the second comparison section.
In one embodiment of the invention, when memory capacities of the first and second memory arrays are different, a memory address storage section for storing an address of a memory array having a smaller memory capacity is provided with a first detection section for detecting whether or not unnecessary upper addresses are specific values.
In one embodiment of the invention, the data transfer control device includes a second determination section for detecting whether or not an address stored in the memory address counter section is a specific value.
In one embodiment of the invention, the first and second memory address storage sections are memory address registers.
According to still another aspect of the present invention, there is provided a semiconductor memory device including the data transfer control device of claim 1.
In one embodiment of the invention, the semiconductor memory device includes an address information storage section for storing address information which is controlled according to an input control command and represents an address targeted for a memory operation including data write, data erase, data read, and data verify operations designated by a control command for operations other than the data transfer operation, and the address information storage section is configured so as to be commonly used with the first or second memory address storage sections required for the data transfer.
According to still another aspect of the present invention, there is provided an electronic information apparatus including the semiconductor memory device of claim 15 which performs a memory operation and a data transfer operation.
Functions of the above-described structure are described below. By commonly using registers for storing address data required for mutual data transfer between the plurality of memory cell arrays provided on a single semiconductor chip so as to simplify a circuit, it is possible to reduce a layout area of the semiconductor chip. Further, since memory address storage means (registers) or the like, which are used for data transfer, can be used for memory operations in addition to the data transfer, it is possible to simplify the circuit, thereby reducing a layout area of a semiconductor chip. Furthermore, it is possible to easily apply the data transfer control device of the present invention to a semiconductor memory device, and further still it is possible to easily apply the same semiconductor memory device to an electronic information apparatus. Therefore, in the semiconductor device or the electronic information apparatus, it is also possible to simplify a circuit for performing a memory operation and a data transfer operation.
Thus, the invention described herein makes possible the advantages of providing: (1) a data transfer control device which can reduce a layout area of a semiconductor chip by commonly using registers for storing address data required for mutual data transfer between a plurality of memory cell arrays provided on a single semiconductor chip so as to achieve simplification of the circuits; (2) a semiconductor memory device including the same data transfer control device; and (3) an electronic information apparatus including the same semiconductor memory device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.